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Dynex

Dynex

Created using Figma
Dynex is a next-generation platform for neuromorphic computing based on a groundbreaking flexible blockchain protocol. It consists of participating nodes that constitute a decentralised neuromorphic supercomputing network which is capable of performing computations at unprecedented speed and efficiency – even exceeding quantum computing.
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Token Details
Ticker
DNX
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About Dynex

By transforming traditional inefficient computers into neuromorphic chips, we will finally be able to create new discoveries. To achieve this, every computer, every laptop and even every mobile device available needs to be connected. As a community and with collaborative effort we can take the next step towards sustainability and efficacy. Transform your phone, your old computer or your dormant mining equipment into neuromorphic machines, earn money and generate wealth.

Our proprietary Dynex Chip design is built based on ideal memristors. Memristors are two-terminal resistive devices with memory. In general, their nonlinear dynamic behaviour is mathematically modeled by means of a differential algebraic equation (DAE) set, in which an ordinary differential equation (ODE) governs the time evolution of the memory state, while an algebraic relation captures the state- and input-dependent Ohm law. The memristor, an acronym for memory resistor, was theoretically introduced in 1971 by L.O. Chua. Introduced in the 1971 pioneering paper, presently referred to as ideal memristor, is the fourth fundamental two-terminal circuit element, the other three being the resistor, the capacitor, and the inductor. Since then, the interest on memristors and their applications has been growing exponentially, with both academia and industry deploying a huge amount of funds and personnel to fabricate, model, and explore the full potential of these devices in electronics applications.

The DynexSolve PoUW algorithm utilises the unprecedented performance of such memristors and performs ODE integration (simulations) of our Dynex Chips. By utilising the massive parallelism of all participating Graphic Processing Units (GPUs), we can achieve close to realtime performance of the original chip design. This allows computations of constraint satisfaction problems, mixed integer linear programming, quadratic unconstraint binary optimisation, maximum satisfiability problem, federated machine learning, efficient pre-training of restricted boltzmann machines and deep neural networks, subset sum problems or integer factorisation.

Participation in events

11 Oct 2025
$
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Whitepaper
dynexcoin.org
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